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checkNodee_Behavioral_VHDL
- LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
LDPCBSN
- LDPC码既低密度奇偶校验码（Low Density Parity Check Code，LDPC），它由Robert G.Gallager博士于1963年提出的一类具有稀疏校验矩阵的线性分组码，不仅有逼近Shannon限的良好性能，而且译码复杂度较低, 结构灵活，是近年信道编码领域的研究热点，目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。LDPC码已成为第四代通信系统(4G) -LDPC codes BER simulation under AWGN channel.
VLSI_Architectures_for_ECC
- This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to sever
Encoders_for_Block_Circulant_LDPC_Codes
- In this paper, we present two encoding methods for block-circulant LDPC codes. The first is an iterative encoding method based on the erasure decoding algorithm, and the computations required are well organized due to the blockcirculant struc
Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror
uart-VHDL
- uart-VHDL 带奇偶校验位 比特率为1152-uart-VHDL add parity check bit rate is 115200
parity_chk_32
- 这是一个32位的奇偶校验程序,VHDL代码,可用于FPGA.-32 bit parity check
parity_chk_32-
- 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check